Field
Embodiments described herein generally relate to methods for depositing materials on a semiconductor substrate. More specifically, embodiments described herein relate to methods for selective depositing utilizing masks and precision materials engineering techniques.
Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density.
As circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 45 nm and 32 nm dimensions and beyond. In order to enable the fabrication of next generation devices and structures, three dimensional (3D) stacking of features in semiconductor chips is often utilized. In particular, fin field effect transistors (FinFETs) are often utilized to form three dimensional (3D) structures in semiconductor chips. By arranging transistors in three dimensions instead of conventional two dimensions, multiple transistors may be placed in the integrated circuits (ICs) very close to each other.
FIG. 1 (prior art) depicts a fin field effect transistor (FinFET) 150 disposed on a substrate 100. The substrate 100 includes a plurality of semiconductor fins 102 formed thereon isolated by shallow trench isolation (STI) structures 104. The shallow trench isolation (STI) structures 104 may be formed by an insulating material.
The substrate 100 may include a portion in an NMOS device region 101 and a portion in a PMOS device region 103 as needed, and each of the semiconductor fins 102 may be sequentially and alternatively formed in the NMOS device region 101 and the PMOS device region 103 in the substrate 100. The semiconductor fins 102 are formed protruding above the top surfaces of the shallow trench isolation (STI) structures 104. Subsequently, a gate structure 106, typically including a gate electrode layer disposed on a gate dielectric layer, is deposited on both of the NMOS device region 101 and the PMOS device region 103 and over the semiconductor fins 102.
The gate structure 106 may be patterned to expose portions 148, 168 of the semiconductor fins 102 uncovered by the gate structure 106. The exposed portions 148, 168 of the semiconductor fins 102 may then be doped with dopants to form lightly doped source and drain (LDD) regions using an implantation process. The patterning process generally utilizes lithographic techniques to form a two dimensional pattern from which 3D structures are created. Often, different surface properties in the two dimensional pattern can increase the complexity of subsequent deposition processes.
Selective deposition processes have been developed to selectively deposit materials on substrates. A conventional method for selective deposition may be performed to locally form a material layer on only certain locations of a planer surface on a substrate made from a material different than the substrate material. FIGS. 2A-2C (prior art) depict an exemplary process utilized to perform the deposition process. The process utilizes self assembled monolayers (SAMs) as a surface modification layer to selectively modify surface properties of the different surface materials exposed on the substrate. For example, a substrate 202 may include a feature 204 formed from a first material (e.g., a silicon oxide layer) disposed on the substrate 202 formed from a second material (e,g., silicon), as shown in FIG. 2A. The feature 204 has an opening 208 defined therein exposing a surface 206 of the substrate 202. SAMs 210 may then be formed on the substrate 202 by a solution based precursor, as shown in FIG. 2B. Generally, the self assembled monolayer (SAM) 210 is formed on the surface that has chemical reaction capability with the molecules from the SAM 210. In the embodiment depicted in FIG. 2B, the precursor utilized to form the SAM 210 is selected to chemically react with a surface 212 of the feature 204, (e.g., a silicon oxide material), rather than the surface 206 of the substrate 202 (e.g., a silicon material). By doing so, the SAM 210 may be predominantly formed on the feature 204 on the substrate 202, leaving the surface 206 of the substrate 202 free of SAM 210. Subsequently, an atomic layer deposition (ALD) process, which is a process highly sensitive to surface conditions, is then performed to form a structure 214 selectively on the designated surface 206 of the substrate 202, as shown in FIG. 2C.
By utilizing the SAM 210 disposed on the features 204, the structure 214 may be formed selectively on only designated surface 206 of the substrate 202. However, in cases when a substrate only contains one type of material, the SAM 210 may be globally formed on the entire surface of such substrate, thereby making the selective material deposition difficult to achieve. In other words, in the case wherein a structure on a substrate is formed by a single type of material, selective deposition via utilization of the SAM may not he successfully enabled, as the self assembled monolayer SAM is to be globally applied without selectivity. For example, the fin structure 102 as depicted in FIG. 1 may be formed by one type of material. However, when only one type of material is desired to be selectively formed or a specific amount of material is desired, utilization of the SAM may not be successful as the SAM may by globally formed on the whole outer surface 120 of the fin structure 102 without selectivity.
Thus, there is a need for improved methods of selective deposition processes.